Low power consumption is a key-feature of mobile devices. Mobile devices now provide video encoding and decoding capabilities that are known to dissipate a lot of energy. So-called low-power video algorithms are thus needed.
As a matter of fact, accesses to an external memory such as SDRAM are a bottleneck for video devices. This is due both to power consumption issues, as memories are known to be the most power-consuming part of a system, and to speed limitation, due to the bandwidth of the exchanges between a central processing unit CPU and the memory.
In conventional video decoders, the motion compensation module needs many such accesses because it constantly points to blocks of pixels in so-called reference frames. To overcome this problem, the international patent application no WO 03/010974 discloses a video decoding device wherein embedded resizing is used in conjunction with external scaling in order to reduce the computational complexity of the decoding.
Such a video decoding device is shown in FIG. 1 and comprises a first path made up of a variable length decoding block VLD, an inverse scan and inverse quantization block ISIQ, an 8×8 inverse discrete cosine transform block IDCT and a decimation block DECI. During operation, the VLD block decodes the incoming video bit-stream at a standard resolution SD to produce motion vectors MV and quantized transformed coefficients. The ISIQ block then inverse scans and inverse quantizes the quantized transformed coefficients received from the VLD block. Further, the IDCT block also performs filtering to eliminate high frequencies from the transformed coefficients. After performing the IDCT, the decimation block then samples the output of the 8×8 IDCT block at a predetermined rate in order to reduce the resolution of the video output frames OF being decoded.
As can be further seen, the decoder also includes a second path made up of the VLD block, a downscaling block DS, a motion compensation unit MC and a frame store MEM. During operation, the downscaling block DS reduces the magnitude of the motion vectors MV provided by the VLD block proportional to the reduction in the first path. This enables memory accesses to be reduced, as the motion compensation is performed at a reduced resolution to match the frames produced in the first path. In addition, the memory size is also reduced, as the stored memory frames are at reduced size.
However, the sequence of output frames is still interlaced, leading to unacceptable artifacts when rendering on a progressive display. Of course a de-interlacing unit could be inserted between the modified decoder and the RGB converter, but at the expense of complexity and memory transfers.